`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/07/05 18:21:10
// Design Name: 
// Module Name: register_ir
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module register_ir(
    clk,reset_n,inst,opcode,funct7,funct3,rs1,rs2,rd
    );

    input clk;
    input reset_n;
    input [31:0] inst;
    output reg [6:0] opcode;
    output reg [2:0] funct3;
    output reg [6:0] funct7;
    output reg [4:0] rd;
    output reg [4:0] rs1;
    output reg [4:0] rs2;

    always @(posedge clk,negedge reset_n) begin
        if(~reset_n) begin
            opcode <= 7'b0;
            rd <= 5'b0;
            funct3 <= 3'b0;
            rs1 <= 5'b0;
            rs2 <= 5'b0;
            funct7 <= 7'b0;
        end
        else begin
            opcode <= inst[6:0];
            rd <= inst[11:7];
            funct3 <= inst[14:12];
            rs1 <= inst[19:15];
            rs2 <= inst[24:20];
            funct7 <= inst[31:25];
        end
    end
endmodule
